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Dr Arshad Aziz
Associate Professor
Department of Electronics and Power Engineering

PNEC
National University of Sciences and Technology (NUST)
NUST–PNEC Habib Ibrahim Rehmatullah Road, Karachi
Tel : 021-48503064, 0333-2228300

Specialization
Reconfigurable Computing, Cryptography, FPGA based System Design, Information Security, Cryptographic Engineering, Software Defined Networking.

Education
PhD in Electrical Engineering, NUST, Pakistan MS in Computer Engineering SSUET, Pakistan B.E. in Computer Engineering, SSUET, Pakistan

Dr Arshad Aziz has been working in the areas of Information Security, FPGA based Digital System Design and Secure Hardware Design since 2000. His work has included research, development, teaching and industrial work at a variety of levels including algorithms, architectures, circuits and methodologies. 

He is currently Associate Professor, Department of Electronic and Power Engineering, National University of Sciences & Technology (NUST-PNEC), Pakistan, where he has been since 1998.
-    Optimal Utilization of available Reconfigurable Hardware Resources
o    Field programmable gate arrays (FPGAs) are continuously gaining momentum and becoming essential part of today’s digital systems and applications. The growing use of these devices coupled with increasingly more complex and integrated designs necessitates search for techniques in efficient utilization of their internal resources. Standard HDL coding techniques and synthesis tools implement logic to look up table (LUT) based architecture. The resulting design utilizes more area on the chip and some fast and dedicated areas and resources of the chip remain unutilized. This in turn results in slower clock rates and larger critical path lengths, hence the design remains inefficient in terms of both speed and area. In this area we present and discuss techniques to effectively utilize the FPGA dedicated resources in order to speed up achievable clock rates and reduce the FPGA area utilization. We develop various useful HDL constructs are presented that utilize dedicated hardware resources of modern Xilinx FPGAs. Optimization techniques that we presented with implementation examples and corresponding quantitative performance evaluation are utilizing 50% less chip area and simultaneously improved timing results significantly.
 
-     Efficient Hardware Implementation of Cryptographic Algorithms on Reconfigurable Platform
o    Optimized implementation of computationally intensive cryptographic primitives is an area of active research. Efficiency of cryptographic algorithm could be greatly improved by applying optimum design methodologies. Mainly focused on Symmetric block cipher and Cryptographic Hash Functions Our work represents a novel efficient S-box designing technique that enhances processing speed and reduces the area required for byte substitution on Xilinx FPGA using Block RAM (BRAM). We also introduced new techniques for critical path minimization using wide input logic functions. The solution enable us to minimize the FPGA inter routing delays between the CLBs and confined the logic to single or minimum number of CLBs where ever possible. The resultant architecture if applied to AES transforms which result in significant resources saving in term of CLB and improve the Throughput Per Slice (TPS) of the design. The design is also applied to develop IEEE 802.11i AES-CCM Core to offload the computational intensive cryptographic processes from main processor thus results in achieving high-speed secure wireless connectivity, thus improving the performance, density and power consumption of the design.
-    We also implemented and investigated the performances of SHA-3 finalists on latest Xilinx FPGAs. We show our results in the form of chip area consumption, throughput and throughput per area on most recently released devices from Xilinx on which implementations have not been reported yet. We have achieved substantial improvements in implementation results from all of the previously reported work. Our work serves as performance investigation of SHA-3 finalists on most up-to-date FPGAs.
-    In our Cryptographic Engineering research we are also focusing on these areas:
•    HW/SW Co-design for Secure Embedded Systems
•    Secure Hardware Design for FPGAs
•    System-on-Chip Integration of Cryptographic Coprocessors
•    Side-Channel Attacks and Fault Attacks on Cryptographic Hardware
•    Performance Evaluation of Cryptographic Hardware and Software
Our work would be beneficial for the hardware implementors specially targeting it for resource constrain environment. Furthermore, the application of crypto system in emerging new resource constrain technologies like IEEE 802.16 and RFID in which performance depends on the area and speed, the results could also be applied in these areas to further improve the performance of resource constrain crypto system.
-    Project: Reconfigurable Software Define Radio
-    The main objective of this research to design software defined radio to have a reconfigurable platform which could be use by any communication standard. Our research area for SDR is to address the issues related with digital front end. Following are the main performance requirements of the digital front end.
-    In this research work we have plan to initially implement different communication standards on FPGA with less resources in terms of LUTS, multipliers and adder units. Then we will exploit the commonalities between the different communication standards and technologies by inspecting their common blocks. At last we combine the functionalities of different communication standards by utilizing bit-level redundancy within the computations. We may also utilize the redundancy in poly-phase/unfolded FIR (Finite Impulse Response) filters or operator level (i.e. sharing adders and multipliers). This would differ from the previous one as that one works on bit-level, while this one would focus on word-level operations and also using the built-in FPGA multipliers. The scope of work may extend to use of fractional delay filters for arbitrary sample rate changes such as Farrow filters in which most things are solved regarding filter design and possibly structures, but not much has been implemented at least not in good way. Designing of multi-standard band selection filters for channelizers would also be a scope of this work.
-    Major optimization of our design will be in the area of:
O    Dynamic Reconfigurability
O    Scalability
O    Initial Design Flexibility 
O    Low Computational Complexity
O    Low Power consumption
O    Low silicon area
 
 
    Biomedical Image Processing on Reconfigurable Platform
o    Prime goal of this research work is to design a real time medical image compression scheme with a high throughput which is computationally less complex without compromising on efficiency. For that we are thump on transform block of encoder with taking full advantage of symmetry of human anatomy in medical images. As a result of this research work, we will able to propose an efficient real time frame work for medical image compression.
o    Medical images such as MRI and CT comprise of noise more than 50% of total image so it is desired to remove noise before further processing of these images. Medical images also have high number of edges. The edge information spreads out in the whole sub band structure which results high frequency sub bands with high energy contents (edge information) and a distribution of non-zero valued coefficients in both low energy sub band and high energy sub bands. This spatial arrangement is difficult and inefficient to code using tree structured inter band coding like SPHIT and EZW. Our approach to improve coding performance is to use Contourlet transform instead of wavelet transform as it always out performs for rich edgy images and provide scalability.
o    We are using hardware software co-design approach, i.e.  Matlab (Software) and FPGA (Reconfigurable computing) in order to achieve our desired goal. MATLAB with its wide range of libraries of functions, demos, block sets and documentation will be very useful in preparation of test bench to check the functionality of algorithm on this platform and then we can implement it on FPGA. We are focusing to use Xilinx Block Sets available in simulink that combines MATLAB, Simulink and XSG (Xilinx System Generator) and explore important features of hardware implementation. Traditional Simulink blocks can be mixed with Xilinx block set to build a complete design. HDL advisor analyzes the Simulink design description and generates both HDL code and an optional bit stream for the targeted FPGA device that is synthesizable in FPGA hardware. In this way we can eliminate weeks of tedious and inefficient work to write HDL code
 
    Embedded Surveillance system
o    The aim of this research work is to design of an embedded automated digital video surveillance system with real-time performance on FPGA. Hardware accelerators for video segmentation, morphological operations, and labeling and feature extraction are required to achieve the real-time performance with the capability of real time tracking. By implementing a complete embedded system, bottlenecks in computational complexity and memory requirements can be identified and addressed.
o    FPGAs have proven to be flexible platform for developing image and video processing applications efficiently due to its high performance parallel processing capability. The proposed work presents an efficient FPGA based architecture for a motion detection algorithm that is capable enough to perform real time video processing and at the same time accumulate the motion detected video resourcefully to reduce the storage. For optimal resource utilization our design has been developed by using LUTS and embedded BRAMS of Xilinx FPGA through Verilog HDL language. The incoming frames from general purpose, low cost analog camera is transformed into bit stream pattern and serially passed to FPGA for further processing. The pixels of each frame are stored in BRAMs in an optimized novel way and then image processing for motion detection is performed on it comparison result clearly show effectiveness of our design in term of FPGA resources. Our proposed architecture can be used in real time application like multimedia, surveillance and smart vision cameras.
 
1.    Zareen Tabassum, Arshad Aziz, Majida Kazmi and Saad Ahmed Qazi “A Robust Wavelet based Digital Image Watermarking technique using FPGA” Mehran University Research Journal of Engineering & Technology Vol.34, No. S1, pp. 139-148, ISSN: 0254-7821 August 2015 [HEC Recognized ‘X’ Category Journal].
 
2.    Saleha Zaka, Arshad Aziz and Dur-e-Shahwar Kundi “Area Efficient S-Box Approach for SubByte Transformation in AES” Mehran University Research Journal of Engineering & Technology Vol.34, No. S1, pp. 63-68, ISSN: 0254-7821 August 2015 [HEC Recognized ‘X’ Category Journal].
 
3.    Dur-e-Shahwar Kundi and Arshad Aziz “Logically Grouped Reduced-set Implementation of SHA3-256 on FPGA” Mehran University Research Journal of Engineering & Technology Vol.34, No. S1, pp. 13-20, ISSN: 0254-7821 August 2015 [HEC Recognized ‘X’ Category Journal].       
 
4.    Dur-E-Shahwar Kundi and Arshad Aziz “Implementation of T-box/T-1-box based AES    design on latest Xilinx FPGA” Mehran University Research Journal of Engineering & Technology, Vol.34, No. 04, pp. 441-446, ISSN: 0254-7821 October 2015 [HEC Recognized ‘X’ Category Journal].
 
5.    Majida Kazmi, Arshad Aziz, Pervez Akhtar and Dur-e-Shahwar Kundi “FPGA Based Compact and Efficient Full Image Buffering for Neighborhood Operations” Advances in Electrical and Computer Engineering,    Vol. 15, No. 1, pp. 95-104, ISSN: 1582-7445, February 2015, [ISI Indexed with Impact Factor (0.529)].    
 
6.    Dur-e-Shahwar Kundi, Arshad Aziz and Majida Kazmi “An Efficient Single unit T-box/T–1-box Implementation for 128-bit AES on FPGA” Security and Communication Networks, John Wiley & Sons, Ltd.  Vol. 8, No, 9, pp. 1725-1731, ISSN: 1939-0114, June 2015, [ISI Indexed with Impact Factor (0.720)].
 
7.    Muzaffar Rao, Thomas Newe and Arshad Aziz “Logically optimized Smallest FPGA Architecture for SHA- 3 Core, Communication Technologies, Information Security and Sustainable Development, Springer Communications in Computer and Information Science, Vol.414, pp. 195-203, ISBN: 978-3-642-28961-2, Springer-Verlag Berlin Heidelberg 2014 [Book Chapter].
 
8.    Munaza Yousuf, Arshad Aziz and Riaz Mahmud, “Area Efficient Implementation of MTI Processing Module on a Re-configurable Platform,” Hindawi Chinese Journal of Engineering, vol. 2013, Article ID 738358, pp 1-7, 2013. doi:10.1155/2013/738358, Hindawi Publishing Corporation 410 Park Avenue  15th Floor, #287 pmb  New York, NY 10022  USA.
 
9.    Alia Arshad, Kanwal Aslam, Dur-e-Shahwar Kundi, and Arshad Aziz “FPGA Implementation of Advance Encryption Standard Using Xilinx System Generator” Asian Journal of Applied Sciences, Vol. 02, No. 02, pp: 190-198, (ISSN: 2321–0893), April 2014 [Scopus Indexed].
 
10.    Irfan Ahmed Usmani, Arshad Aziz, Muzaffar Rao and Razia Zia “Comparison between FPGA Logic Resources and Embedded Resources Used By Discrete Arithmetic (DA) Architecture to Design FIR Filter” International Journal of Scientific Engineering and Technology Volume No.3 Issue No.4, pp: 440-443, (ISSN: 2277-1581), 1 April 2014 [Ulrich Indexed].
 
11.    Muhammad Abubakar, Arshad Aziz and Pervez Akhtar “Xilinx System Generator® Based Implementation of a Novel Method of Extraction of Nonstationary Sinusoids” Journal of Signal and Information Processing, Scientific Research Publishing Inc, USA. Vol. 4, pp 7-13, October 2013 ISSN: 2159-4465 [Ulrich Indexed]
 
12.    Salman Sadruddin and Arshad Aziz, “Reduced Precision Redundancy for Satellite Telecommand Receiver Module on FPGA,” Hindawi Chinese Journal of Engineering, vol. 2013, Article ID 738358, pp 1-8, 2013. doi:10.1155/2013/738358, Hindawi Publishing Corporation 410 Park Avenue  15th Floor, #287 pmb  New York, NY 10022  USA.
 
13.    Razia Zia, Muzaffar Rao, Arshad Aziz and Pervez Akhtar "Efficient Utilization of FPGA using LUT-6 Architecture" Industrial Instrumentation and Control Systems Applied Mechanics and Materials Trans Tech Publications CH-8635 Zurich-Durnten Switzerland Vols. 241-244, pp 2548-2554, 2013 ISBN-13:978-3-03785-546-1  [Book Chapter].
 
14.    Syed Muhammad Adnan and Arshad Aziz “Efficient Hardware Implementation of SHA-3 Candidate Grøstl using FPGA" International Journal of Computer Applications Published by Foundation of Computer Science, New York, USA ISSN: 0975–8887, pp 6-11, Vol. 55 No. 14, October 2012. [Ulrichsweb Indexed].
 
15.    Kashif Latif, Arshad Aziz and Athar Mahboob "Look-Up Table Based Implementations of SHA-3 Finalisits: JH, Keccak and Skein" KSII Transactions on Internet and Information Systems Vol. 6, No. 9, pp 2388-2404, September 2012 ISSN : 1976-7277 [ISI     Indexed with Impact Factor(0.560)].
 
16.    Kashif Latif, Arshad Aziz, Athar Mahboob, “Hardware Performance Evaluation of SHA-3 Finalists - Blake, Keccak and Skein”, Arab Gulf  Journal of Scientific Research Vol. 30, No.1, pp. 14-20,  ISSN: 10154442, March 2012.[ISI indexed with Impact Factor(0.047)].
 
17.    Kashif Latif, M Muzaffar Rao, Athar Mahboob and Arshad Aziz, “Novel Arithmetic Architecture for High Performance Implementation of SHA-3 Finalist Keccak on FPGA Platforms”, In: O.C.S. Choy et al. (Editors), Proceedings of ARC2012, Reconfigurable Computing: Architectures, Tools and Applications, Lecture Notes in Computer Science, Vol. 7199, pp. 372–378, ISBN: 978-3-642-28365-9, Springer-Verlag Berlin Heidelberg 2012 [Book Chapter]..
 
18.    M Muzaffar Rao, Kashif Latif, Arshad Aziz and Athar Mahboob, “Efficient FPGA Implementation of Secure Hash Algorithm Grøstl – SHA-3 Finalist”, In: Proceedings of IMTIC’12, Springer Communications in Computer and Information Science, Vol. 281, pp. 361–372, ISBN: 978-3-642-28961-3, Springer-Verlag Berlin Heidelberg 2012 [Book Chapter].
 
19.    Kashif Latif, Muhammad Tariq, Arshad Aziz and Athar Mahboob, “Efficient Hardware Implementation of Secure Hash Algorithm (SHA-3) Finalist - Skein”, In: Proceedings of 3CA2011, Advances in Intelligent and Soft Computing 2012, Vol. 133 pp. 933-940 ISBN: 978-3-642-27552-4 Springer Lecture Notes in Electrical Engineering, ISSN: 1876-1100, November 2011 [Book Chapter].
 
20.    Kashif Latif, Muhammad Tariq, Arshad Aziz and Athar Mahboob “High Throughput Hardware Implementation of Secure Hash Algorithm Skein-256” International Journal of Academic Research (IJAR), Baku, Azerbaijan, Vol. 3, No.6, part II, pp.313-317,ISSN: 2075-4124, November 2011. [ISI Indexed]
 
21.    Kashif Latif, Muhammad Tariq, Arshad Aziz and Athar Mahboob “Efficient Software Implementation of Secure Hash Algorithm (SHA-3) Candidate-Skein” International Journal of Academic Research (IJAR), Baku, Azerbaijan, Vol. 3, No.6, part I, pp.200-206, ISSN: 2075-4124, November 2011. [ISI Indexed]
 
22.    Pervez Akhter, Tariq Javid and Arshad Aziz “Some Aspects of Deposition Parameters of RF Some Aspects of Deposition Parameters of RF Some Aspects of Deposition Parameters of RF” Advanced Materials Research (AMR), Advances in Materials and Processing Technologies II Trans Tech Publications CH-8635 Zurich-Durnten Switzerland Vols. 264 – 265, pp 160-165, ISBN-13: 978-3-03785-053-4, February 2011. [ISI Indexed]
 
23.    Kashif Latif, Arshad Aziz and Athar Mahboob “Optimal Utilization of Available Reconfigurable Hardware Resources” Elsevier Computers & Electrical Engineering, Vol. 37, No. 6, pp. 1043-1057, ISSN: 0045-7960, November 2011. [ISI Indexed with Impact Factor (0.837)]
 
24.    Dur-e-Shahwar Kundi, Arshad Aziz and Nassar Ikram “Resource Efficient Implementation of T-Boxes in AES on Virtex-5 FPGA” Elsevier Information Processing Letters (IPL), Vol.110, Issue No.10, pp 373-377, ISSN: 0020-0190, 30 April 2010 [ISI Indexed with Impact Factor (0.612)].
 
25.    Arshad Aziz and Nassar Ikram “Memory Efficient Implementation of AES S-boxes on FPGA” Journal of Circuits, Systems and Computers (JCSC). Vol. 16, No. 4, pp. 603-611, ISSN: 0218-1266, August 2007[ISI indexed with Impact Factor (0.130)].
 
26.    Arshad Aziz and Nassar Ikram “An FPGA-based AES-CCM Crypto Core for IEEE802.11i Architecture” International Journal of Network Security (IJNS), Vol. 5, No. 2, pp. 224-232, ISSN: 1816-353X, September 2007. [Scopus Indexed]
 
27.    Arshad Aziz and Nassar Ikram, “Firewall for the Security of E-Commerce Infrastructure” published in Journal of Science & Technology PNEC, NUST, Karachi, Pakistan, Vol.1,   pp. 41-45, ISSN: 1728-5690, June 2004.
 
28.    Arshad Aziz “Bluetooth Wireless Networking” published in Journal of Science & Technology PNEC, NUST, Karachi, Pakistan, Vol.1,   pp. 70-71, ISSN: 1728-5690, June 2001.
 
CONFERENCE PAPERS

29.    Jamal Ahmed, Arshad Aziz and Pervez Akhtar “FPGA based Efficient Architecture for Image Watermarking using Wavelet Coefficients Quantization "IEEE 2014 International Conference on Open Source Systems and Technologies (ICOSST 2014), pp. 105-112, ISBN: 978-1-4799-2053-2, 18-20 December 2014, Lahore Pakistan.
 
30.    Munaza Yousuf, Riaz Mahmud and Arshad Aziz “Simulation Design of an Efficient MTI Processing Module for Embedded Platform” IEEE 2nd Mediterranean Conference on Embedded Computing (MECO 2013) June 16-20, 2013, Budva, Montenegro.
 
31.    Alia Arshad, Dur-e-Shahwar Kundi, and Arshad Aziz “Compact Implementation of SHA3-512 on FPGA” IEEE Conference on Information Assurance and Cyber Security 2014 (CIACS-2014), 12-14 June 2014, Rawalpindi, Pakistan ISBN: 978-1-4799-5852-8.
 
32.    Shoaib Mughal and Arshad Aziz “High Level Implementation of DES” International Conference on Engineering & Emerging Technologies 2014 (ICEET-2014) 20-21 March 2014, Lahore Pakistan.
 
33.    Jamal Ahmed and Arshad Aziz “Xilinx System Generator Based Pipelined Architecture for Image Watermarking using Wavelet Co-efficient Quantization" IEEE 2014 International Conference on Open Source Systems and Technologies (ICOSST 2014), ISBN: 978-1-4673-3095-4, 18-20 December 2014, Lahore Pakistan.
 
34.    Alia Arshad, Dur-e-Shahwar Kundi, and Arshad Aziz “Compact Implementation of SHA3-512 on FPGA” IEEE Conference on Information Assurance and Cyber Security 2014 (CIACS-2014), 12-14 June 2014, Rawalpindi, Pakistan ISBN: 978-1-4799-5852-8.
 
35.    Muhammad Arsalan, Muhammad Ata-ur-Rehman, Nasir Mehmood and Arshad Aziz “Compact Hardware Implementation of SHA-3 Finalist Blake on FPGA” 2013 IEEE 9th International Conference on Emerging Technologies (ICET-2013) pp. 1-5, December 9-10 2013, Islamabad Pakistan ISBN: 978-1-4799-3457-7.
36.    Shoaib Mughal and Arshad Aziz “High Level Implementation of DES” International Conference on Engineering & Emerging Technologies 2014 (ICEET-2014) 20-21 March 2014, Lahore Pakistan.
 
37.    Muzaffar Rao, Thomas Newe and Arshad Aziz “Logically optimized Smallest FPGA Architecture for SHA- 3 Core In: Proceedings of Third International Multi-topic Conference, IMTIC 2013, Jamshoro, Pakistan, December 18—20, 2103,.
 
38.    Munaza Yousuf, Riaz Mahmud and Arshad Aziz “Simulation Design of an Efficient MTI Processing Module for Embedded Platform” IEEE 2nd Mediterranean Conference on Embedded Computing (MECO 2013) June 16-20, 2013, Budva, Montenegro.
 
39.    Arshad Aziz, Dur-e-Shahwar and Salman Mubin “Efficient Implementation of KECCAK (SHA-3) Algorithm on FPGA” 2013 International Conference of Information Security and Internet Engineering, Proceedings Book of World Congress on Engineering 2013 Vol. II, ISBN: 978-988-19252-8-2, London, U.K., 2-4 July, 2013.
 
40.    Aisha Malik, Arshad Aziz, Dur-e-Shahwar Kundi and Moiz Akhter “Software Implementation of Standard Hash Algorithm (SHA.3) Keccak on Intel Core.i5 and Cavium Networks Octeon Plus Embedded Platform” IEEE 2nd Mediterranean Conference on Embedded Computing (MECO 2013) June 16-20, 2013, Budva, Montenegro.
 
41.    Aisha Malik, Arshad Aziz and Abdul Qadeer, “Implementation of SHA-3 Candidate Skein on Two Unexplored Multiprocessor Platforms” IEEE 2013 International Conference on Sensor Network Security Technology and Privacy Communication System (IEEE SNS & PCS-2013) ISBN: 978-1-4673-6452-2, pp 193-196, 18-19 May 2013, Harbin, China.
 
42.    Muhammad Arsalan and Arshad Aziz "Low-Cost Machine Vision System for Dimension measurement of Fast Moving Conveyor Products" IEEE 2012 International Conference on Open Source Systems and Technologies (ICOSST 2012), ISBN: 978-1-4673-3095-4, 20-22 December 2012, Lahore Pakistan
 
43.    Syed Muhammad Adnan and Arshad Aziz "Resource Efficient and Area Optimized GrØstl Implementation on FPGA" IEEE 2012 International Conference on Open Source Systems and Technologies (ICOSST 2012), ISBN: 978-1-4673-3095-4, 20-22 December 2012, Lahore Pakistan.
 
44.    Muhammad Arsalan and Arshad Aziz "Comparative Analysis of high speed and low area architectures of Blake SHA-3 candidate on FPGA" IEEE 10th International Conference on Frontier in Information Technology FIT-12, pp. 248 - 253 , ISBN: 978-0-7695-4927-9, 17-19 December, 2012, Serena Hotel, Islamabad, Pakistan. 
 
45.    Majida Kazmi, Arshad Aziz, Pervez Akhtar, Aliza Maftun, Wasay Bin "Medical Image Denoising based on Adaptive Thresholding in Contourlet Domain" IEEE  5th International Conference on BioMedical Engineering and Informatics (BMEI'12)  from 16-18 October 2012, in Chongqing, China, pp 219-224, ISBN:978-1-4244-6514-9, [EICompendex Indexed].
 
46.    Hudaisa Afzal, Kinza Shafique, Zubair Ahmed Junaid, Syed Hassan Raza Naqvi, Arshad Aziz "Implementation of Segmentation on FPGA for LTE Transmission" 2012 International Conference on Electrical Engineering and Computer Science,16 to 19 August, 2012 - Shanghai, China
 
47.    Kashif Latif, Arshad Aziz, Athar Mahboob and M Muzaffar Rao, “Efficient Hardware Implementations and Hardware Performance Evaluation of SHA-3 Finalists”, In: 3rd SHA-3 Candidate Conference, March 2012, Washington DC, USA.
 
48.    Dur-e-Shahwar Kundi and Arshad Aziz “Compact Implementation of Skein-256 Hash Function on FPGA” IEEE the Spring World Congress on Engineering and Technology (SCET2012), pp, 1-4, ISBN: 978-1-4577-1965-3 May 27-30 2012, Xian China.
 
49.    Kashif Latif, Athar Mahboob, Arshad Aziz “High Throughput Hardware Implementation of Secure Hash Algorithm (SHA-3) Finalist: BLAKE” IEEE 9th International Conference on Frontier in Information Technology FIT-11, pp 189-194, ISBN: 978-0-7695-4625-4, 16-18 December, 2011, Serena Hotel, Islamabad, Pakistan. 
 
50.    Shezana Zulfiqar Ali, Azka Khalil, Sumayyah Waheed, and Arshad Aziz “MATLAB Simulation of a Variable Speed Controller for a Three Phase Induction Motor” 26th IEEEP Annual Multi-topic International Symposium (SIMTS-2011) 16-17 March, 2011 Pearl Continental Hotel, Karachi, Pakistan.
 
51.    Jamal Ahmed, Muhammad Faisal and Arshad Aziz “FPGA Based High Quality Video Acquisition System” 26th IEEEP Annual Multi-topic International Symposium (SIMTS-2011) 16-17 March, 2011 Pearl Continental Hotel, Karachi, Pakistan.
 
52.    Nighat Jamil and Arshad Aziz “Wavelet Transformation based Image Authentication and Codec Independent Video Authentication” IEEE 8th International Bhurban Conference on Applied Sciences & Technologies (IBCAST 2011) 10-13 January 2011 Pakistan ISBN: 978-1-4244-6514-9.
 
53.    Ursila Khan and Arshad Aziz “An Efficient Implementation of SPIHT Algorithm on a Reconfigurable Hardware” IEEE 8th International Bhurban Conference on Applied Sciences & Technologies (IBCAST 2011), pp-69-73, 10-13 January 2011 Pakistan ISBN: 978-1-4244-6514-9.
 
54.    Qurat-Ul-Ain and Arshad Aziz “FPGA Based Secure Architecture for Medical Imaging” IEEE 8th International Bhurban Conference on Applied Sciences & Technologies (IBCAST 2011) 10-13 January 2011 Pakistan ISBN: 978-1-4244-6514-9.
 
55.    Nighat Jamil and Arshad Aziz “A Unified Approach to Secure and Robust Hashing Scheme for Image and Video Authentication” IEEE 3rd International Congress on Image and Signal Processing 2010. (CISP 2010), pp. 274-278, 16 – 18 October 2010, China ISBN: 978-1-4244-6514-9, [EI Compendex Indexed].
 
56.    Majida Islam, Arshad Aziz and Pervez Akhter “Secure Transfer of Digital Images– DICOM” 25th IEEEP Annual Multi-topic International Symposium (SIMTS-2010) 17-18 March, 2010 Pearl Continental Hotel, Karachi, Pakistan.
 
57.    Kashif Latif. Arshad Aziz and Athar Mahboob “Efficient Resource Utilization of FPGAs” ACM 7th International Conference on Frontier in Information Technology FIT-09, December 16-18, 2009, CIIT, Abbottabad, Pakistan.  Article No.: 26, ACM 978-1-60558-642-7/09/12. NY USA.
 
58.    Pervez Akhtar, Tariq Javed  Ali and Arshad Aziz  “Some Aspects of Deposition Parameters of RF Sputtered Ferromagnetic Film Germane to the Study of Magnetoresistive Sensing Devices ”International Conference on Advances in Materials and Processing Technologies 2009 (AMPT2009), Kuala Lumpur, Malaysia, 26 - 29 October 2009.
 
59.    Tariq Javed Ali, Arshad Aziz, Pervez Akhtar and Muhammad Iqbal Bhatti “A Framework for Secure Access to Medical Images” 2009 IEEE International Conference on Bioinformatics, Computational Biology, Genomics and Chemoinformatics (BCBGC-09), Orlando, FL, USA during July 13-16 2009, pp 15-19, ISBN: 978-1-60651-009-4.
 
60.    Dur-e-Shahwar Kundi, Saleha Zaka, Qurat-Ul-Ain and Arshad Aziz “A Compact AES Encryption Core on Xilinx FPGA”, In proceedings of 2nd IEEE International Conference on Computer, Control & Communication (IEEE IC4-2009) 17- 18 February 2009, Karachi, Pakistan, pp 1-4, ISBN: 978-1-4244-3313-1.
 
61.    Tariq Javed Ali, Pervez Akhtar, Arshad Aziz “Modeling and Simulation of Network and Systems Service Management in a Typical Modern Healthcare Organization”,  In: 5th International conference on Innovations in Information Technology (Innovations'08), 16 - 18 December 2008, Al Ain, UAE.
 
62.    Abdul Samiah, Arshad Aziz and Nassar Ikram “An Efficient Software Implementation of AES-CCM For IEEE 802.11i Wireless Standard”  in IEEE 31st Annual International Computer Software and  Applications Conference(COMPSAC 2007) , Vol. 2, pp. 689-694, ISBN 978-0-7695-2870-0, Beijing, China, July 24-27, 2007.
 
63.    Arshad Aziz and Nassar Ikram “A Look-Up-Table Implementation of AES,” in International Conference on High Performance Computing, Networking and Communication Systems (HPCNCS-07), pp. 187-191, ISBN 978-0-9727412-5-5, Orlando Florida, USA, July 9-12 2007.
 
64.    Arshad Aziz and Nassar Ikram “A High Throughput Implementation of AES on a Low Cost FPGA”  in proceedings of  IEEE Workshop of 2005 International Conference on Computational Intelligence and Security (CIS 2005), pp. 605-609,  ISBN 3-540-30819-9, Xi’an, China, December 15-19 2005.
 
65.    Arshad Aziz and Nassar Ikram “An Efficient FPGA based Sequential Implementation of Advanced Encryption Standard” in proceedings of IEEE ITI 3rd International Conference on Information and Communication Technology (ICICT 2005), pp. 875-882, ISBN: 0-7803-9270-1, Cairo, Egypt, December 5-6 2005.
 
66.    Arshad Aziz and Nassar Ikram “Hardware Implementation of AES-CCM for Robust Secure Wireless Network” Proceedings of the 5th Annual ISSA Information Security Conference (ISSA 2005), pp. 44 -51, ISBN 1-86854-625X, Johannesburg, South Africa, July 2005.
 
67.    Arshad Aziz, Abdul Samiah and Nassar Ikram, “A Secure Framework for Robust Secure Wireless Network (RSN) using AES-CCMP” Proceedings of 4th International Bhurban Conference on Applied Sciences & Technologies (IBCAST 2005), Vol. 2, pp. 11-18. ISSN: 969-8741-03-08, Bhurban, Pakistan, June 11-18 2005

 
Over 17 years of teaching experience at NUST, Karachi, Pakistan

Courses taught:
-    Advanced Digital System Design
-    Networking Protocols    
-    Internetworking
-    Network Security    
-    Network Management
-    Fundamental of Cryptography    
-    Applied Cryptography
-    Advanced Digital System Design    
-    Reconfigurable Computing        
-    Advanced FPGA Design
-    Communication Security
-    Reconfigurable Communication Systems
-    Cryptographic Engineering
-    Computer Communication and Networks
-    Microprocessor based system design
-    Information Security
Over 8 years of industry work experience in the area of networking at NUST-PNEC provided design and implementation procedure for Network projects. Performed System maintenance and Network administration on a Fast Ethernet LAN network with Giga Speed Fiber Optics Backbone and Nortel Networks Passport 1150 core switch, Fast Ethernet Manageable Bay Stack 450 Switches & Nortel, 3Com, Intel, SMC Hubs. Maintain, 6 Windows 2003 & Windows 2000 Servers, SUN Ultra Sparc, Silicon Graphic Workstation, 400 Windows XP, 2000, Windows NT& WIN98 workstations, Novell NetWare 3.12 network and 1000+ users Directory database. Carried out repair and maintenance of all computer peripherals. Created thorough technical documentation for technicians and suppliers.
 
-    Designed and implemented campus wide LAN integration with Giga Speed Fiber Optics Backbone infrastructure for 600+ node network.
-    Designed and implemented high-speed campus wide Internet connection through satellite.
-    Designed and implemented WAN link between Karachi and Islamabad campuses of NUST through VPN.
-    Implemented MS Windows 2008/2003, DNS, WINS DHCP, MS IIS, MS ISA, MS Proxy, MS Exchange 2008/2003, MS SQL and Oracle servers.
-    Designed and implemented campus wide Instant Messaging and online Video conferencing.
-    Implemented complete network management and monitoring system using SNMP, MRTG and Fluke LAN Inspector.
-    Designed and implemented disaster recovery plan and techniques using ARC server 2008 for backup and Symantec Ghost Enterprise Edition for client side deployment.
-    Implemented Remote Accesses and Remote Management using Windows 2008 Terminal services and Symantec PC Anywhere 11.5.
-    Implement Centralized Anti-Virus, Scanning, Quarantine and Update system using Symantec Antivirus 10.0 /12.0 Cooperate Edition.
-    Designed and maintained in house Hardware repair facility.