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Dr Dur-e-Shahwar Kundi
Assistant Professor
Department of Electronics and Power Engineering

National University of Sciences and Technology (NUST)
NUST–PNEC Habib Ibrahim Rehmatullah Road, Karachi
Tel : 021-48504798, 0321-2297022

Cryptography, Information Security, FPGA based System Design, Cryptographic Engineering, Reconfigurable Computing.

PhD in Electrical Engineering, NUST, Pakistan.  M.S. in Electrical Engineering (Specialization: Communication Engg.), NUST, Pakistan. B.E. in Electrical Engineering, NUST, Pakistan.

​Dr. Dur-e-Shahwar has been working in the area of Cryptography, Information Security and FPGA based Digital System Design since 2008. Her work has included research and teaching at a variety of levels including algorithms, architectures, circuits and methodologies. She is currently Assistant Professor at Department of Electronic and Power Engineering, National University of Sciences & Technology (NUST-PNEC) Pakistan, where she has been since 2007.

Apart from research and teaching, she is also involved in administrative part also. She is OIC Digital Electronics Lab, R & D co-ordinator EPE department, Course officer and as an Internal Auditor.
​-   Efficient hardware implementation of Cryptographic primitives:
-   Efficient AES Architectures Supporting Confidentiality
-   Efficient SHA-3 Architectures Supporting Integrity
-   Efficient Unified Architecture for both confidentiality and integrity

     Cryptographic Engineering:
    Build efficient AES and SHA-3 architectures with respect to the internal architectural design of selected reconfigurable hardware i.e. FPGA
1.    Dur-e-Shahwar Kundi and Arshad Aziz, “A Low-power SHA-3 Designs Using Embedded Digital Signal Processing Slice on FPGA”, Elsevier Journal of Computers & Electrical Engineering, vol. 55, pp. 138–152 (Oct 2016). [ISI indexed IF=0.817]
2.    Dur-e-Shahwar Kundi, Arshad Aziz and Nassar Ikram, “A High Performance ST-Box Based Unified AES Encryption/Decryption Architecture on FPGA”, Elsevier Journal of Microprocessor & Microsystems, vol. 41, pp. 37-46 (2016) [ISI indexed IF 0.43] 
3.    Dur-e-Shahwar Kundi, Arshad Aziz and Kashif Latif, “Resource Efficient Implementation of Keccak, Skein & JH Algorithms on Reconfigurable Platform”, C¸ankaya University Journal of Science and Engineering, vol. 13, no.1, pp. 40-57 (2016). [ISI indexed]
4.    Dur-e-Shahwar Kundi, Arshad Aziz and Majida Islam, “An Efficient Single Unit T-box/T-1-box Implementation for 128-bit AES on FPGA”, Wiley Journal of Security & Communication Networks vol. 8, no. 1, pp. 1725–1731, doi: 10.1002/sec.1138 (2015) [ISI indexed IF 0.72]
5.    Majida Kazmi, Arshad Aziz, Pervaiz Akhtar and Dur-e-Shahwar Kundi, “FPGA Based Compact and Efficient Full Image Buffering for Neighborhood Operations”, Advances in Electrical and Computer Engineering, vol. 15, no. 1, pp. 95-104, doi:10.4316/AECE.2015.01014 (2015) [ISI indexed IF 0.54]
6.    Dur-e-Shahwar Kundi and Arshad Aziz, “Logically Grouped Reduced-set Implementation of SHA3-256 on FPGA”, Mehran University Journal of Science & Engineering (MUJSE), vol. 34, Special issue 1, pp. 13-15 (2015) [HEC recognized X category]

7.    Dur-e-Shahwar Kundi and Arshad Aziz, “Implementation of T-box/T-1-box based AES design on latest Xilinx FPGA”, Mehran University Journal of Science & Engineering (MUJSE), vol. 34, no. 4, pp. 441-446 (2015) [HEC recognized X category]

8.    Saleha Zaka, Arshad Aziz and Dur-e-Shahwar Kundi, “Area Efficient S-Box Approach for SubByte Transformation in AES”, Mehran University Journal of Science & Engineering (MUJSE), vol. 34, Special issue 1, pp. 63-68 (2015) [HEC recognized X category]

9.    Alia Arshad, Kanwal Aslam, Dur-e-Shahwar Kundi and Arshad Aziz, "FPGA Implementation of Advance Encryption Standard Using Xilinx System Generator", Asian Journal of Applied Sciences, vol. 02, pp.190-198 (2014)  [Scopus Indexed]

10.    Alia Arshad, Dur-e-Shahwar Kundi and Arshad Aziz, “Compact implementation of SHA3-512 on FPGA”, IEEE Conference on Information Assurance and Cyber Security (CIACS 2014), pp. 29-33, 2014, Islamabad, Pakistan.

11.    Aisha Malik, Arshad Aziz, Dur-e-Shahwar Kundi and Moiz Akhter, "Software Implementation of Standard Hash Algorithm (SHA.3) Keccak on Intel Core.i5 and Cavium Networks Octeon Plus Embedded Platform", IEEE 2nd Mediterranean Conference on Embedded Computing (MECO 2013), vol. 1, pp. 79-83, 2013, Budva, Montenegro.

12.    Dur-e-Shahwar Kundi and Arshad Aziz, "Compact Implementation of Skein-256 Hash Function on FPGA", IEEE Spring World Congress on Engineering and Technology (S-CET 2012), pp. 1-4, May 27-30 2012, Xian China.

13.    Dur-e-Shahwar Kundi, Arshad Aziz and Nassar Ikram, "Resource Efficient Implementation of T-Boxes in AES on Virtex-5 FPGA", Elsevier Information Processing Letters (IPL), vol. 110 no.10, pp.373-377 (2010) [ISI indexed IF 0.58]

14.    Dur-e-Shahwar Kundi, Saleha Zaka, Qurat-Ul-Ain and Arshad Aziz, "A Compact AES Encryption Core on Xilinx FPGA", IEEE 2nd International Conference on Computer, Control & Communication (IC4-2009), vol. 1, pp.1-4, 2009, Karachi, Pakistan.

15.    Dur-e-Shahwar Kundi, Adnan Farid, “PLC Based Smart Lifting System Using Pneumatics”, 23rd IEEEP Multi-Topic International Symposium, 28-29 March, 2008, Karachi.
​Over 10 years of teaching experience at NUST, Karachi, Pakistan

Courses taught:

•    Linear Circuit Analysis
•    Digital System Design
•    Basic Electrical Engineering
•    Industrial Electronics
•    Power Distribution & Utilization
•    Power Transmission
•    Electrical Analysis-II
•    Electronic Devices and Circuits